Stanford DG645 Digital delay and pulse generator
(4 or 8 ch.) (Distributed only in Germany.)
Operation
Delay Generator Timing
All digital delay generators measure time intervals by counting cycles of a fast clock (typically 100 MHz). Most digital delay generators also have short programmable analog delays to achieve time intervals with finer resolution than the clock period. Unfortunately, one clock cycle of timing indeterminacy (typically 10 ns) can occur if the trigger is not in phase with the clock.
The DG645 eliminates timing indeterminacy by measuring the timing of triggers with respect to the internal clock and compensating the analog delays. This approach reduces the jitter by about 100× and allows the internal rate generator to operate at any rate — not just a sub-multiple of the clock frequency.
